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Mr. Bonifus P L
B.Tech. in Electronics & Communication, M.Tech.(Electronics) with Specialization in VLSI & Embedded Systems.
Asst. Professor

Bonifus P L received his Electronics & Communication Engineering degree from College of Engineering Poonjar under Cochin University of Science & Technology (2007) and M.Tech (Electronics) with specialization in VLSI & Embedded Systems from TKM Institute of Technology under Cochin University of Science & Technology (2012). He has 2.4 years of industrial experience as Software Developer at Mahindra Satyam, Hyderabad and became Microsoft Certified Professional on May 2008. He joined Rajagiri School of Engineering & Technology in the year 2012 and his areas of interest are VLSI design and Embedded Systems.

Industry: 2 Years and 4 Months - 29 October 2007 to 18 March 2010 – Software Developer, Mahindra Satyam, Hyderabad

20 June 2012 to till date – Asst. Professor, Rajagiri School of Engineering & Technology, Kochi

RSET Unique Id: 31651
Area of Interest: VLSI & Embedded Systems
Email bonifus@rajagiritech.edu.in
ORCID_iD https://orcid.org/0000-0001-5656-6001
Google Scholar ID https://scholar.google.co.in/citations?user=jzkcY74AAAAJ&hl=en
Website people.rajagiritech.ac.in/bonifus
Year Title of the Paper-Conference/Journal Details
2022 Optimisation of FPGA-Based Designs for Convolutional Neural Networks
Comprises of select peer-reviewed papers presented during the 18th Control Instrumentation System Conference
2019 Study and Implementation of Ethernet Based Synchronization in Distributed Data Acquisition System
International Conference on Computer Networks and Inventive Communication Technologies,Springer
ICTRCET - 2018
2017 An efficient built-in self-repair scheme for multiple RAMs, 2nd IEEE RTEICT
2016 Design and Analysis of Modified Fast Compressors for MAC Unit, International Journal of Computer Trends and Technology (IJCTT) – Volume 36 Number 4 - June 2016
2016 Design of AES Architecture With Area and Speed Tradeoff, Procedia Technology Volume 24, 2016, Pages 1135-1140
2015 "Implementation of FFT Butterfly Algorithm Using SMB Recoding Techniques" IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 5, Ver. I (Sep - Oct. 2015), PP 00-00, e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197
2015 Area Optimized Architecture for AES Mix Column Operation International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181, Vol. 4 Issue 09, September-2015
2014 Dual mode logic based adder for energy efficient, high performance CMOS structures
2014 Dual Mode Logic and Sleepy Stack: Design for Energy Efficient, High Performance and Leakage Reduced CMOS Structures
2014 Implementation of Algorithm for Selection of Convenient Route for Blind Pedestrian On Raspberry Pi
2013 ECC Encryption System Using Encoded Multiplier and Vedic Mathematics
2013 RSA Encryption System Using Encoded Multiplier and Vedic Mathematics
Year Date of Publication Title of the Book Published By Edition
2022 12-Mar-2023 Smart Sensors Measurement and Instrumentation/ Optimisation of FPGA-Based Designs for Convolutional Neural Networks Springer, Singapore 1